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This conversation presents the reflections from five prominent disaster scholars and practitioners on the purpose of Radix – the Radical Disaster Interpretations network – as the authors celebrate its 20th anniversary.

This paper is based on the conversations that took place on Disasters: Deconstructed Podcast livestream on the 13th October 2021.

The conversation reflects on personal and professional journeys in disaster studies over the past 20 years and on what needs changing in order to make disaster interpretations more radical.

The conversation contributes to the ongoing discussions around explorations of radical pathways for understanding and preventing disasters.

This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.

A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.

With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.

This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

In recent years, multiuser-multiple-input multiple-output (MU-MIMO)-based wireless communication system has emerged as a prominent 5G technique that has several advantages over conventional MIMO systems such as high data rate and channel capacity. In this paper, the authors introduce a novel low-complexity radix factorization-based fast Fourier transform (FFT) as a multibeamformer and maximal likelihood-MU detection (ML-MUD) techniques as an optimal signal subdetector which results with considerable complexity reduction with intolerable error rate performance.

The proposed radix-factorized FFT-multibeamforming (RF-FFT-MBF) architectures have the potential to reduce both hardware complexity and energy consumptions as compared to its state-of-the-art methods while meeting the throughput requirements of emerging 5G devices. Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors.

Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors. Through experimental results, it is well proved that the proposed detector offers significant hardware and energy efficiency with the least possible error rate performance overhead.

Here through simulation results, the efficiency of the scaled ML subdetector system is compared with the conventional ML detectors. Through experimental results, it is well proved that the proposed detector offers significant hardware and energy efficiency with the least possible error rate performance overhead.

In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.

The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.

A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.

This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

The use of ten as a radix for everyday numbering seems to be a suitable compromise. Non‐decimal numbers have applications in error detection and in computing. In the latter, it is interesting that there has been competition between octal and hexadecimal formats for manual interaction, and one reason for the prevalence of the latter is attributed to the use of seven‐line character displays and an improbable feature of this in relation to the English alphabet.

The suggested work examines the latest developments such as the techniques employed for allocation of power, browser techniques, modern analysis and bandwidth efficiency of nonorthogonal multiple accesses (NOMA) in the network of 5G. Furthermore, the proposed work also illustrates the performance of NOMA when it is combined with various techniques of wireless communication namely network coding, multiple-input multiple-output (MIMO), space-time coding, collective communications, as well as many more. In the case of the MIMO system, the proposed research work specifically deals with a less complex recursive linear minimum mean square error (LMMSE) multiuser detector along with NOMA (MIMO-NOMA); here the multiple-antenna base station (BS) and multiple single-antenna users interact with each other instantaneously. Although LMMSE is a linear detector with a low intricacy, it performs poorly in multiuser identification because of the incompatibility between LMMSE identification and multiuser decoding. Thus, to obtain a desirable iterative identification rate, the proposed research work presents matching constraints among the decoders and identifiers of MIMO-NOMA.

To improve the performance in 5G technologies as well as in cellular communication, the NOMA technique is employed and contemplated as one of the best methodologies for accessing radio. The above-stated technique offers several advantages such as enhanced spectrum performance in contrast to the high-capacity orthogonal multiple access (OMA) approach that is also known as orthogonal frequency division multiple access (OFDMA). Code and power domain are some of the categories of the NOMA technique. The suggested research work mainly concentrates on the technique of NOMA, which is based on the power domain. This approach correspondingly makes use of superposition coding (SC) as well as successive interference cancellation (SIC) at source and recipient. For the fifth-generation applications, the network-level, as well as user-experienced data rate prerequisites, are successfully illustrated by various researchers.

The suggested combined methodology such as MIMO-NOMA demonstrates a synchronized iterative LMMSE system that can accomplish the optimized efficiency of symmetric MIMO NOMA with several users. To transmit the information from sender to the receiver, hybrid methodologies are confined to 2 × 2 as well as 4 × 4 antenna arrays, and thereby parameters such as PAPR, BER, SNR are analyzed and efficiency for various modulation strategies such as BPSK and QAM_j (j should vary from 8,16,32,64) are computed.

The proposed hybrid MIMO-NOMA methodologies are synchronized in terms of iterative process for optimization of LMMSE that can accomplish the optimized efficiency of symmetric for several users under different noisy conditions. From the obtained simulated results, it is found, there are 18%, 23% 16%, and 8% improvement in terms of Bit Error Rate (BER), Least Minimum Mean Squared Error (LMMSE), Peak to Average Power Ratio (PAPR), and capacity of channel respectively for Binary Phase Shift Key (BPSK) and Quadrature Amplitude Modulation (QAM) modulation techniques.

Apart from direct revelation, all communication demands that something be done, something be recognized, and that an agreed something else be done about it when recognized. In other words, communication takes place through artificially induced physical events, interpreted in action according to artificial rules. There are two essential aspects, the physical and the conventional, of every process and type of communication, from engraving epitaphs to measuring photographs. Each of Faust's attempts to translate Logos was valid.

This paper describes and discusses aspects that affect research questions in a practice-based research study, where learning study is used as a framework. The purpose of this paper is to contribute to understanding of the process where teachers and a researcher collaborate in transforming practical teaching problems into research questions.

A case study is conducted. Data consist of field notes, logbooks, manuscripts and conference papers from two learning studies conducted in grade 4 by three teachers and one researcher, and notes from meetings in a subject-teacher group at the school. The analysis focuses on how the research questions emerge and change in relation to discussions among teachers and in the research group of teaching, previous research and learning theory.

Questions about students’ discernment of the structure in the base-ten system emerged in learning study 1 and in the subject-teacher group. Discussions of previous research and the didactical theory learning activity transformed the research questions in learning study 2, into focusing students’ theoretical knowledge, examining general structures in the base system, using learning models as tools. Conditions for identification of specific teaching problems and alternative theory in a learning study are discussed.

The explicit example where research questions are transformed can be used in further discussions and methodological questions regarding formulation of research questions in educational research. Discussions, specifically of transforming research questions, when learning study is used may be promoted.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

All of the above proposals are realities in Western Europe, and it is suggested that the adoption of such “reforms” would substantially reduce the transaction costs of providing compensation to deserving plaintiffs, improve the efficiency of the tort system, and provide manufacturers and service providers with greater predictability and “fairness” in potential tort damages in the United States.