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This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.

The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.

In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.

The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit.

This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library.

Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA.

The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

This study aims to reveal the essential characteristics of nonstationary signals and explore the high-concentration representation in the joint time–frequency (TF) plane.

In this paper, the authors consider the effective TF analysis for nonstationary signals consisting of multiple components.

To make it, the authors propose the combined multi-window Gabor transform (CMGT) under the scheme of multi-window Gabor transform by introducing the combination operator. The authors establish the completeness utilizing the discrete piecewise Zak transform and provide the perfect-reconstruction conditions with respect to combined TF coefficients. The high-concentration is achieved by optimization. The authors establish the optimization function with considerations of TF concentration and computational complexity. Based on Bergman formulation, the iteration process is further analyzed to obtain the optimal solution.

With numerical experiments, it is verified that the proposed CMGT performs better in TF analysis for multi-component nonstationary signals.

Unmanned aerial vehicles are commonly known as UAVs and drones. Nowadays, industries have begun to realise the operational and economic benefits of drone-enabled tasks. The Internet of Things (IoT), Big Data, drones, etc., represent implementable advanced technologies intended to accomplish Industry 4.0. The purpose of this study is to discuss the significant contributions of drones for Industry 4.0.

Nowadays, drones are used for inspections, mapping and surveying in difficult or hazardous locations. For writing this paper, relevant research papers on drone for Industry 4.0 are identified from various research platforms such as Scopus, Google Scholar, ResearchGate and ScienceDirect. Given the enormous extent of the topic, this work analyses many papers, reports and news stories in an attempt to comprehend and clarify Industry 4.0.

Drones are being implemented in manufacturing, entertainment industries (cinematography, etc.) and machinery across the world. Thermal-imaging devices attached to drones can detect variable heat levels emanating from a facility, trigger the sprinkler system and inform emergency authorities. Due partly to their utility and adaptability in industrial areas such as energy, transportation, engineering and more, autonomous drones significantly impact Industry 4.0. This paper discusses drones and their types. Several technological advances and primary extents of drones for Industry 4.0 are diagrammatically elaborated. Further, the authors identified and discussed 19 major applications of drones for Industry 4.0.

This paper’s originality lies in its discussion and exploration of the capabilities of drones for Industry 4.0, especially in manufacturing organisations. In addition to improving efficiency and site productivity, drones can easily undertake routine inspections and check streamlines operations and maintenance procedures. This work contributes to creating a common foundation for comprehending Industry 4.0 outcomes from many disciplinary viewpoints, allowing for more research and development for industrial innovation and technological progress.

Over the past few decades, lean manufacturing has focussed on being customer-centred and now Lean 4.0 technologies have made it possible for manufacturers to have a deeper view of waste reduction. Technologies such as the internet of things, artificial intelligence, three-dimensional printing, robotics, real-time data, cloud computing, predictive analytics and augmented reality, are helpful to achieve Lean 4.0. This study aims to develop the conceptual understanding of Lean 4.0, related tools and linkage with Industry 4.0. Further, it provides the strategies for implementing Lean 4.0, developing lean culture and highlights the Lean 4.0 application in the manufacturing context.

This study relates to Lean 4.0 and its technologies. Prominent research is identified through Scopus, Web of Science, ScienceDirect and Google Scholar and studied as per the objective of this study. This lean revolution provides customers desire for personalisation, connectedness, high-quality and valuable products. Lean 4.0 provides valuable information on the value chain and production process. This revolution has significantly impacted refining production processes for a greater level of adaptability and cost reduction.

This paper is brief about Lean 4.0 and its capabilities for the reduction of waste. The authors discussed different tools used in Lean 4.0 and its relationship with Industry 4.0. The classical strategies and progressive features of Lean 4.0 for overall enhancing the manufacturing sphere are discussed diagrammatically. Finally, it identified and discussed 14 significant applications of Lean 4.0 for manufacturing industries.

This study provides a comprehensive understanding of Lean 4.0 and related tools and strategies that help the upcoming manufacturing industries.

The purpose of this study is to evaluate the possibility of utilization of pomegranate seed powder and tomato powder in the development of fiber-enriched chicken nuggets.

The study was designed to incorporate and evaluate the effect of pomegranate seed powder and tomato powder on the quality characteristics of the chicken nuggets. The products were developed by incorporating different levels of pomegranate seed powder (1, 2, 3 per cent) and tomato powder (1, 2, 3 per cent) separately and were analyzed for various physicochemical and sensory parameters.

The pomegranate seed powder and tomato powder significantly (p < 0.05) increased the fiber content of the chicken nuggets besides improving various sensory attributes of the products. A significant (p < 0.05) effect of the pomegranate seed powder was observed on the pH, emulsion stability, cooking yield and proximate parameters of the chicken nuggets. Tomato powder also showed a significant (p < 0.05) effect on the emulsion stability, moisture and fat content of the products. No significant (p > 0.05) effect of tomato was observed on the pH and cooking yield of the products.

Fiber-enriched chicken nuggets could be developed by incorporating pomegranate seed powder and tomato powder in the formulation besides improving various sensory attributes of the products.