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This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.

The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.

Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.

The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

This paper aims to implement a novel design of approximate comparator which can be suitable for image processing applications.

Here, the N-bit approximate comparator is implemented by taking reference of N as 2-, 4- and 8-bit. The design analyses the fractional change in error to bit in several bit formats. The final implementation of approximate comparator design application compares the structural similarity index, colour test and extraction of an image to the results.

The novel approximate comparator was designed using 2-, 4- and 8-bit to explore N-bit comparator expressions. The implementation, computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively. The computations, evaluation of errors, applications and the design constraints were executed using Python and Synopsys, respectively.

This paper presents the N-bit accurate and approximate comparator which is novel over the existing design of comparators.